The present invention relates to digital signal processing, and more particularly to a number format conversion apparatus for signal processing that supports a variety of fixed and floating point number formats, converting between formats as needed in a signal processing path.
Most digital signal processing is done with signals represented in the form of a series of numerical samples expressed in a fixed point binary number format. The popularity of this format is due to the relative ease with which the most common signal processing operations may be realized in hardware, such as addition, subtraction, comparison and multiplication. Other advantages of this number format that make signals easy to control include good control over rounding errors, a fixed limited range, and a constant resolution over the entire range.
However the fixed range and constant resolution are also great disadvantages for many of the less common signal processing operations, such as squares, square roots, logarithms, exponentials and divides. In order to maintain precision in the result, each of these operations requires either a large expansion or contraction of word size for the numerical samples if a fixed number format is used. For example squaring a sixteen bit number produces a result requiring 32 bits. For these cases, therefore, a floating point number format is more appropriate. Unfortunately it is much more difficult to implement addition, subtraction and comparison operations for a floating point number format, so much so that it would become prohibitively expensive to do so in many cases.
Often in a digital signal processing environment the magnitude of a vector or imaginary number representing a signal is desired. To determine the magnitude two orthogonal vector components are derived from respective signal sources, providing digital integer number values. The integer values are each squared, the squares summed, and the square root of the result is obtained, usually from a read only memory lookup table. Since the read only memory has a limited number of inputs, it is desired to convert the sum of the squares to a floating point number. To take the square root the exponent of the floating point number needs to be limited so that the number of bits that access the lookup table is not excessive. This requires added circuitry to determine the size of the exponent and to limit and shift.
Another example in the digital video effects environment is reverse addressing when determining which combination of pixels from an input frame of a video image needs to be accessed to provide a corresponding pixel at the output. This requires three sources that provide digital integer numbers. The numbers from two of the sources are divided by the number from the third source, which requires converting to a floating point number format. To get the two addresses from the results requires converting back to a fixed point number format. Previously specific circuitry was required for each type of number format.
What is needed is hardware that supports a variety of fixed and floating point number formats, converting between number formats as needed in a signal processing path.